发明名称 DELAY LINE AND DELAY CONTROL METHOD
摘要 The present invention relates to a delay circuit and a delay control method. The delay circuit includes transmission gates connected in a parallel; a look-up table generating unit generating a look-up table indicating information on turn-on combination of the transmission gates corresponding to linear delay steps; and a control code generation unit generating a control code for controlling the transmission gates by using the generated information on the turn-on combination of the look-up table. [Reference numerals] (110) User interface unit; (120) Control code generation unit; (130) Look-up table generating unit; (140) Storage unit; (AA) Input signal; (BB) Output signal
申请公布号 KR101383223(B1) 申请公布日期 2014.04.14
申请号 KR20120091899 申请日期 2012.08.22
申请人 发明人
分类号 H03K5/13;H03L7/081 主分类号 H03K5/13
代理机构 代理人
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