| 摘要 |
Disclosed is an apparatus for synchronization of data and clock in a memory tester, which delays a phase of input data to a location where a setup/hold time is guaranteed such that the data can be always accurately latched in serdes. In the disclosed apparatus for synchronization of data and clock in a memory tester, the memory tester comprises: a host terminal outputting pattern data and commands for testing a memory, and a pattern generation board which tests the memory according to a control command of the host terminal; and a communication controller for controlling communication between the pattern generation board (PGB) and the host terminal. The pattern generation board includes an input data protocol converter and a serial input processing unit for converting serial data, output from the communication controller, into parallel data and transmitting the converted data to an algorithm pattern generator (ALPG). The serial input processing unit receives specific pattern data repeated in serial communication to measure a phase of data and a current clock, and delays a phase of input data to a location, where a setup/hold time is guaranteed, by using the measured phase value such that the data and the clock can be synchronized. [Reference numerals] (301) Input delayer; (302) SERDES; (303) Byte aligner; (304) Delay value calculator |
