发明名称 MEMORY CONTROLLER, INFORMATION PROCESSOR, AND MEMORY CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To improve the utilization efficiency of a bus when a read access based on identical bank identification information continuously occurs in a memory mirror configuration.SOLUTION: A memory controller 501 controls access to a memory which is divided into a plurality of operation units. A first operation unit and second operation unit, out of the plurality of operation units, constitute a memory mirror. A reception unit 511 receives a plurality of read requests that include bank identification information for both a first bank that is included in the first operation unit and a second bank that is included in the second operation unit. A determination unit 512 determines an access target for each read access so that a plurality of read accesses based on the plurality of read requests are performed alternately for the first operation unit and second operation unit. A control unit 513 controls each of the read requests so that each of the read accesses is performed for the operation unit determined as the access target.
申请公布号 JP2014063299(A) 申请公布日期 2014.04.10
申请号 JP20120207347 申请日期 2012.09.20
申请人 FUJITSU LTD 发明人 HARA SOJI
分类号 G06F12/06 主分类号 G06F12/06
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