| 摘要 |
PROBLEM TO BE SOLVED: To achieve the improvement of the performance of a stream access and the reduction of power consumption in an arithmetic processing unit.SOLUTION: The arithmetic processing unit includes a cache writing processing queue for registering a writing processing request to a cache memory based on a store instruction issued by an instruction issuing part in an entry with a stream weight flag, and for outputting a writing processing request with a stream weight flag in a non-set state from among the registered writing processing requests to a pipe line processing part which performs pipeline processing to the cache memory. When the stream flag added to the store instruction is set, it is determined that there exists a following store instruction to the same data region as the pertinent store instruction, and the stream weight flag is put in a set state, and the writing processing request is registered in the entry, and the writing processing requests based on the store instruction to the same data region are stored in a batch in one writing processing request. |
