发明名称 Testing a Hardware Emulation Model of a Circuit with Software Checker Routines Designed for an RTL Model of the Circuit
摘要 A hardware emulation system may emulate a plurality of cycles of a circuit, and may store state information at each cycle which specifies signal values for one or more signals of the circuit. After the hardware emulation has finished, the state information may be streamed from the memory of the hardware emulation system to a different storage device that is accessible by a computer system that executes one or more software checker routines. The computer system may execute the software checker routines, which may include passing the signal values specified in the state information to the software checker routines on a cycle-by-cycle basis similarly as if the software checker routines were receiving them in real time directly from the hardware emulation system.
申请公布号 US2014100841(A1) 申请公布日期 2014.04.10
申请号 US201213647742 申请日期 2012.10.09
申请人 APPLE INC. 发明人 BURES EDMOND R.;LENT JEFFREY V.;BOEHM FRITZ A.
分类号 G06F17/50 主分类号 G06F17/50
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