| 摘要 |
Provided is a shift register capable of being driven using various clock signals, with low power consumption. A bistable circuit (SR) of a shift register is provided with first to third transistors (Tr1-Tr3), first to third input terminals (11-13), and an output terminal (21). In the first transistor (Tr1), a gate terminal thereof and a first conduction terminal thereof are connected to the first input terminal (11). In the second transistor (Tr2), a gate terminal thereof is connected to the third input terminal (13), and a first conduction terminal thereof is connected to the first input terminal (11). In the third transistor (Tr3), a gate terminal thereof is connected respectively to second conduction terminals of the first and second transistors (Tr1, Tr2), a first conduction terminal thereof is connected to the second input terminal (12), and a second conduction terminal thereof is connected to the output terminal (21). |
