发明名称 SERIALIZER-DESERIALIZER CLOCK AND DATA RECOVERY GAIN ADJUSTMENT
摘要 In described embodiments, a VCO based CDR for a SerDes device includes a phase detector, a VCO responsive to a first control signal and a second control signal and generating an output signal, a frequency calibration module configured to calibrate the frequency of the output signal by performing a coarse calibration and a subsequent fine calibration, a gear shifting control module controlling a gain, change of the first and second control signals in time, and a look-up table created by fine calibration values generated from the frequency calibration module, wherein the programmed variable gain of the gear shifting control module is calculated by a calculation circuit employing the fine calibration values stored in the look-up table, the calculation of the calculation circuit adjusts gear shifting down, and adjusts a gear shifting gain, and adjusting an overall CDR gain over a VCO control curve.
申请公布号 US2014097878(A1) 申请公布日期 2014.04.10
申请号 US201213647470 申请日期 2012.10.09
申请人 LSI CORPORATION 发明人 SINDALOVSKY VLADIMIR;ANIDJAR JOSEPH;SMITH LANE A.;HARDY BRETT DAVID
分类号 H03L7/08 主分类号 H03L7/08
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