| 摘要 |
PROBLEM TO BE SOLVED: To provide a data processing apparatus which can enhance performance of the whole apparatus by reducing a load on a host CPU.SOLUTION: An arithmetic unit 10 comprises: an SIMD processor 14 which processes a plurality of pieces of data by a single instruction; a second CPU 11 which is connected with the SIMD processor 14 through a bus 13 for an arithmetic unit and controls the SIMD processor 14; and a boot circuit 16 that performs boot processing of the second CPU 11. A host system 20 comprises: a host CPU 21 which controls an entire data processing apparatus 1; and a built-in memory 22 and a peripheral circuit 24 which are connected with the host CPU 21 through a first bus 23. The second CPU 11 performs boot processing by executing an instruction that is output from the boot circuit 16; and the host CPU 21 performs boot processing by executing an instruction that is stored in the built-in memory 22. |
