| 摘要 |
A configuration of logic elements enables existing Serial-In-Parallel-Out (SIPO) shift registers to perform their own bit count, report the receipt of a valid transmission consisting of an expected number of bits and report the receipt of an invalid transmission consisting of greater than the expected number of bits. Logic elements additional to the foregoing enable SIPO shift registers to receive valid transmissions of varying expected numbers of bits. Special purpose integrated circuits (ICs) are disclosed which also contain the aforementioned configurations of logic elements. Newly designed SIPO shift registers which contain within them the foregoing configurations of logic elements are further disclosed. Potential messages of multiple acceptable message lengths are accommodated. Some embodiments are equipped with tri-state data outputs. |
