发明名称 DEVICE FOR IDENTIFICATION OF CATASTROPHIC FAILURES IN BASIC MEMORY CIRCUITS ON ELEMENTS AND-NOT
摘要 A device for identification of catastrophic failures in basic memory circuits includeselements AND-NOT, one of the inputs of the elements is connected to the input bus of installation of memory circuit to one of states when the memory circuits are divided intogroups, and when the memory circuits are divided intogroups the other input of the system of AND-NOT elements is connected to input bus for storage of the states of memory circuit, the groups include arbitrary number q of not connected to each other by output elements AND-NOT, at that the inputs of the elements AND-NOT of any group are connected to the output of each element AND-NOT of other groups, respectively. For control of serviceability of the memory circuit against catastrophic failures a control circuit is additionally included, for the memory circuits on the elements AND-NOT on five elements : AND-NOT (1) the inputs of which are connected to the units of input bus of memory circuit setting; AND-NOT (2) input units of that one are connected to the units of output memory bus of the output bus of the memory circuit; AND (3) where one output unit is connected to the output unit AND-NOT (2), and the other input units are connected to the units of output bus of memory circuit; AND (4) where one input unit is connected to the output unit of the element AND-NOT (1), and the other input units are connected to the units of the output bus of the memory circuit; OR (5) the input units of which are connected to the output units of the elements AND (3) and (4); the output unit of the element OR (5) connected to the output bus of the control circuit.
申请公布号 UA88895(U) 申请公布日期 2014.04.10
申请号 UA20130010272U 申请日期 2013.08.21
申请人 Мараховський Леонід Федорович;Москвін Максим Вікторович;Москвін Вадим Вікторович;Осадча Ганна Андрієвна 发明人 Мараховський Леонід Федорович;Москвін Максим Вікторович;Москвін Вадим Вікторович;Осадча Ганна Андрієвна
分类号 F15C1/10 主分类号 F15C1/10
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