DELAY LOCKED LOOP AND CLOCK GENERATION METHOD

摘要

The present invention relates to a delay locked loop and a clock generation method, wherein the delay locked loop comprises: a ring oscillator which includes a delay line for generating a delay clock signal by delaying a reference clock signal, circulates a feedback clock signal corresponding to the delay clock signal to the delay line, and synchronizes an N (N is an integer of 2 or more) cycle of the feedback clock signal to one cycle of the reference clock signal; and a first frequency divider for generating an output clock signal by dividing a frequency of the delay clock signal by 1/N (N is an integer of 2 or more) times. [Reference numerals] (110) Delay line; (120) Signal selecting unit; (130) Delay control unit; (140) First frequency divider; (150) Dummy delay unit; (AA) Reference clock signal; (BB) Delay signal; (CC) Input clock signal; (DD) Control code; (EE) Delay clock signal; (FF) Feedback clock signal; (GG) Output clock signal