发明名称 Max-log-map equivalence log likelihood ratio generation soft viterbi architecture system and method
摘要 A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.
申请公布号 US8694877(B2) 申请公布日期 2014.04.08
申请号 US20100924707 申请日期 2010.10.01
申请人 PARTHASARATHY SIVAGNANAM;HUANG LUN BIN;RISSO ALESSANDRO;STMICROELECTRONICS, INC. 发明人 PARTHASARATHY SIVAGNANAM;HUANG LUN BIN;RISSO ALESSANDRO
分类号 H03M13/03 主分类号 H03M13/03
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