| 摘要 |
<p>The present invention relates to a shift register capable of successfully outputting a scan pulse by preventing charge leakage when the duty ratio of the scan pulse is low. The shift register includes a plurality of stages for outputting a carry pulse and a scan pulse. The n^th element (n: natural number) includes: a carry output switching element which is controlled according to the voltage applied to a set node and is connected between a carry clock transmitting line for transmitting one among carry clock pulses of the i^th phase (i: natural number greater than 1) and the carry output terminal of the n^th stage; a scan output transmitting switching element which is controlled according to the voltage applied to the set node and is connected between a scan clock transmitting line for transmitting one among scan clock pulses of the j^th phase (j: natural number greater than 1) and the carry output terminal of the n^th stage; and a stabilization switching element which is controlled according to a carry clock pulse which is overlapped with a scan clock pulse applied to the scan output switching element and is connected between the carry output terminal of the (n-p)^th stage (p: natural number smaller than n) and the set node or between a start transmitting line for transmitting a start pulse and the set node.</p> |
