| 摘要 |
Provided is a manufacturing method for a substrate for a chip package including a step of arranging a thin insulating layer and a bonding layer at an angle between 10° and 20° to a virtual horizontal plane (X) formed by a boundary surface between upper and lower rollers to be laminated; a step of forming a through-hole penetrating the thin insulating layer and the bonding layer; and a step of forming a circuit pattern layer on the bonding layer. |
