METHOD AND APPARATUS TO SCHEDULE STORE INSTRUCTIONS ACROSS ATOMIC REGIONS IN BINARY TRANSLATION
摘要
<p>A method and system to support scheduling of memory store instructions across atomic regions in binary translation in a processing unit or processor. In one embodiment of the invention, the processing unit has a store buffer that allows store instructions to be issued in different order than the source binary program order but still retire in source binary program order. This facilitates a small atomic region that maps to each iteration of a source binary code and these atomic regions are joined together into a pipelined region. In one embodiment of the invention, the processing unit executes commit instruction(s) once every loop iteration instead of executing the commit instruction(s) once after the loop exit.</p>
申请公布号
WO2014047828(A1)
申请公布日期
2014.04.03
申请号
WO2012CN82139
申请日期
2012.09.27
申请人
INTEL CORPORATION;MA, GUOKAI;JIN, YIHUA;LAVERY, DANIEL M.;LI, JIANHUI
发明人
MA, GUOKAI;JIN, YIHUA;LAVERY, DANIEL M.;LI, JIANHUI