发明名称 CACHE CONTROL DEVICE AND PIPELINE CONTROL METHOD
摘要 A cache control device includes an entering unit, a first searching unit, a reading unit, a second searching unit, and a rewriting unit. The entering unit alternately enters, into a pipeline, a load request for reading a directory received from a processor and a store request for rewriting a directory received from the processor. When the first searching unit determines that the directory targeted by the load request is present in the first cache memory or the second cache memory, the reading unit reads the directory from the cache memory in which the directory is present. When the second searching unit determines that the directory targeted by the store request is present in the first cache memory, the rewriting unit rewrites the directory that is stored in the first cache memory.
申请公布号 US2014095792(A1) 申请公布日期 2014.04.03
申请号 US201314097306 申请日期 2013.12.05
申请人 FUJITSU LIMITED 发明人 HATAIDA MAKOTO;ISHIZUKA TAKAHARU;YAMAMOTO TAKASHI;HOSOKAWA YUKA
分类号 G06F12/08 主分类号 G06F12/08
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