摘要 |
<p>Systems, apparatuses, and methods of performing in a computer processor broadcasting data in response to a single vector packed broadcasting instruction that includes a source writemask register operand, a destination vector register operand, and an opcode. In some embodiments, the data of the source writemask register is zero extended prior to broadcasting.</p> |
申请人 |
INTEL CORPORATION;HUGHES, CHRISTOPHER J.;CHARNEY, MARK J.;CORBAL, JESUS;GIRKAR, MILIND B.;OULD-AHMED-VALL, ELMOUSTAPHA;TOLL, BRET L.;VALENTINE, ROBERT |
发明人 |
HUGHES, CHRISTOPHER J.;CHARNEY, MARK J.;CORBAL, JESUS;GIRKAR, MILIND B.;OULD-AHMED-VALL, ELMOUSTAPHA;TOLL, BRET L.;VALENTINE, ROBERT |