发明名称 |
METHOD OF SHARING AND RE-USING TIMING MODELS IN A CHIP ACROSS MULTIPLE VOLTAGE DOMAINS |
摘要 |
A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of the chip includes a macro abstract instantiated in a voltage domain different from the domain during abstract generation. Timing models are re-used across chip voltage domains or across chip designs. Moreover, a statistical timing analysis of a chip design takes into consideration the voltage domains wherein at least one timing abstract model generation time voltage domain condition differs from the macro instantiation domain in the chip. The invention further provides sharing and re-using the statistical timing models or abstracts. |
申请公布号 |
US2014096100(A1) |
申请公布日期 |
2014.04.03 |
申请号 |
US201213633911 |
申请日期 |
2012.10.03 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
SINHA DEBJIT;FLUHR ERIC J.;SHUMA STEPHEN G.;VENKATESWARAN NATESAN;VISWESWARIAH CHANDRAMOULI;WOOD MICHAEL H.;ZOLOTOV VLADIMIR |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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