| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory system device architecture capable of a high speed operation.SOLUTION: A memory system includes: memory devices mutually connected in series, and each memory device receives a clock signal. The clock signal can be provided to the entire memory devices in parallel, or from a memory device to a memory device through a common clock input in series. A clock mode configuration circuit of each memory device is set to a parallel mode for receiving a parallel clock signal, or a series mode for receiving a source synchronous clock signal from the preceding memory device. A data input circuit is formed to be a corresponding data signal format, and a corresponding clock input circuit is enabled or disabled in accordance with a set operation mode. The parallel mode and the series mode are set by sensing the voltage level of reference voltage provided to each memory device. |
