发明名称 |
GENERATING AN EQUIVALENT WAVEFORM MODEL IN STATIC TIMING ANALYSIS |
摘要 |
A method is provided for use during static timing analysis of an integrated circuit design to produce an equivalent waveform model, the method comprising: using an analog model of the inner component, to simulate an inner component to produce multiple analog simulation output characterization waveforms as a function of multiple input waveforms used to characterize the design cell; using the analog model of the inner component to simulate the inner component to produce an analog simulation output waveform as a function of the complex waveform; and producing the equivalent waveform model as a function of the multiple analog simulation output characterization waveforms and the analog simulation output waveform. |
申请公布号 |
US2014096099(A1) |
申请公布日期 |
2014.04.03 |
申请号 |
US201213632885 |
申请日期 |
2012.10.01 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
PHILLIPS JOEL R.;LIU QUNZENG;KELLER IGOR |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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