| 摘要 |
Disclosed is a read timing generation circuit, capable of reducing dynamic power consumption. After a multi-bit address Add1, Add2, . . . , and AddN passes through an address change monitoring unit (100), a response pulse signal corresponding the address is generated. After the response pulse signal passes through an address trigger determination unit (200), a single trigger determination signal ATDPRE is generated. The single trigger determination signal ATDPRE passes through an ATD timing generation unit (300) and a post-timing generation unit (1000), thereby forming a read timing generation circuit in a serial link and generating corresponding read timing. Compared with the conventional read timing generation circuit in which each bit of an address signal corresponds to a stage of structures to execute the trigger, ATD control timing output, and ATD determination process separately, the present invention greatly reduces the total dynamic power consumption of the circuit. |
