发明名称 |
SYSTEM AND METHOD FOR CHEMICAL-MECHANICAL PLANARIZATION OF A METAL LAYER |
摘要 |
A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes depositing a low-k inter-metal layer over a semiconductor substrate, depositing a porogen-containing low-k layer over the low-k inter-metal layer, and etching a space for the via through the low-k inter-metal layer and the porogen-containing low-k layer. The method further includes depositing a metal layer, a portion of the metal layer filling the space for the via, another portion of the metal layer being over the porogen-containing low-layer, removing the portion of the metal layer over the porogen-containing layer by a CMP process, and curing the porogen-containing low-k layer to form a cured low-k layer. |
申请公布号 |
US2014091477(A1) |
申请公布日期 |
2014.04.03 |
申请号 |
US201213631684 |
申请日期 |
2012.09.28 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COM. LTD.;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
WU YUNG-HSU;FU SHIH-KANG;YAO HSIN-CHIEH;LIN CHIA-MIN;LEE HSIANG-HUAN;LEE CHUNG-JU;CHEN HAI-CHING;SHUE SHAU-LIN |
分类号 |
H01L23/48;H01L21/306;H01L21/66 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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