| 摘要 |
An integrated circuit (100) comprises a clock generation stage (120) arranged to generate a clock signal having a clock frequency dependent on a reference signal. A delay stage (130) is arranged to generate a delayed clock signal by delaying the clock signal. A control stage (140) is arranged to generate a control signal indicative of a delay of the delayed clock signal relative to the clock signal. A frequency divider (150) arranged to generate a divided signal by dividing a dividend signal having a dividend frequency dependent on the reference signal. A power supply regulator (170) is arranged to supply power to the frequency divider (150) at a first power level, the first power level being dependent on the control signal. |
