发明名称
摘要 <p>Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.</p>
申请公布号 JP5456643(B2) 申请公布日期 2014.04.02
申请号 JP20100255319 申请日期 2010.11.15
申请人 发明人
分类号 G06F9/305 主分类号 G06F9/305
代理机构 代理人
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地址