Increasing efficiency of memory accesses by selectively introducing a relative delay between the time that write addresses are provided to the memory and the time that write data is provided to the memory

摘要

Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.