发明名称 Gather cache architecture
摘要 Apparatuses and methods to perform gather instructions are presented. In one embodiment, an apparatus comprises a gather logic module which includes a gather logic unit to identify locality of data elements in response to a gather instruction. The apparatus includes memory comprising a plurality of memory rows including a memory row associated with the gather instruction. The apparatus further includes memory structure to store data element addresses accessed in response to the gather instruction.
申请公布号 US8688962(B2) 申请公布日期 2014.04.01
申请号 US201113078380 申请日期 2011.04.01
申请人 RAIKIN SHLOMO;VALENTINE ROBERT;INTEL CORPORATION 发明人 RAIKIN SHLOMO;VALENTINE ROBERT
分类号 G06F9/30 主分类号 G06F9/30
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