发明名称 |
System and method for asynchronously and independently controlling core clocks in a multicore central processing unit |
摘要 |
A method of controlling core clocks in a multicore central processing unit is disclosed and may include executing a zeroth dynamic clock and voltage scaling (DCVS) algorithm on a zeroth core and executing a first DCVS algorithm on a first core. The zeroth DCVS algorithm may operable to independently control a zeroth clock frequency associated with the zeroth core and the first DCVS algorithm may be operable to independently control a first clock frequency associated with the first core. |
申请公布号 |
US8689037(B2) |
申请公布日期 |
2014.04.01 |
申请号 |
US20100944321 |
申请日期 |
2010.11.11 |
申请人 |
RYCHLIK BOHUSLAV;IRANLI ALI;SALSBERY BRIAN J.;SUR SUMIT;THOMSON STEVEN S.;GLENN ROBERT A.;QUALCOMM INCORPORATED |
发明人 |
RYCHLIK BOHUSLAV;IRANLI ALI;SALSBERY BRIAN J.;SUR SUMIT;THOMSON STEVEN S.;GLENN ROBERT A. |
分类号 |
G06F1/04;G06F1/12;G06F5/06 |
主分类号 |
G06F1/04 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|