发明名称 Control circuit and data hold device using the control circuit
摘要 A control circuit 10 includes an internal clock generating portion (12), which starts generating an internal clock signal (LCLK) required by a control portion (11) to perform action when a specific signal pattern appears in a trigger signal, continually generates the internal clock signal (LCLK) at least before the control portion (11) completes predetermined processing, and then stops generating the internal clock signal (LCLK); and the control portion (11), which uses the internal clock signal (LCLK) to perform the predetermined processing.
申请公布号 US8686774(B2) 申请公布日期 2014.04.01
申请号 US201113332558 申请日期 2011.12.21
申请人 KIMURA HIROMITSU;ICHIDA YOSHINOBU;ROHM CO., LTD. 发明人 KIMURA HIROMITSU;ICHIDA YOSHINOBU
分类号 H03K3/00 主分类号 H03K3/00
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