发明名称 |
Analog frontend for CCD/CIS sensor |
摘要 |
A system for signal processing comprising a cyclic analog to digital converter structure having a first stage and a second stage, wherein the first stage is configured to receive an input signal to perform 1.5 bits/stage ADC and to generate a first stage output signal, and the second stage is configured to receive the first stage output signal and to perform fine offset tuning using a final conversion phase. The second stage further configured to perform 1.5 bits/stage ADC and to generate a second stage output that is fed back to the first stage to iteratively generate a next 1.5 bits, until (N−3) most significant bits of N bits of data are generated. A third stage configured to generate a three least significant bits of the N bits of data using a flash ADC sampling circuit that samples a residue signal at the output of the first stage. |
申请公布号 |
US8686889(B2) |
申请公布日期 |
2014.04.01 |
申请号 |
US201213618443 |
申请日期 |
2012.09.14 |
申请人 |
REDDY CHANDRASHEKAR A.;VADAPALLI YAGNESHWARA RAMAKRISHNA RAO;CONEXANT SYSTEMS, INC. |
发明人 |
REDDY CHANDRASHEKAR A.;VADAPALLI YAGNESHWARA RAMAKRISHNA RAO |
分类号 |
H03M1/38 |
主分类号 |
H03M1/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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