| 摘要 |
Disclosed are an apparatus and method for maintaining cache coherency and a multiprocessor apparatus using the same. The multiprocessor apparatus according to the present invention includes a main memory, a plurality of processors, a plurality of cache memories connected to each processor, a memory bus which is connected to the main memory and the cache memories, and a coherency bus which is connected to the cache memories and transmits coherency related information between caches. Thereby, an insufficient bandwidth phenomenon generated by using a communication structure between the memory and the cache is reduced in an on-chip communication structure and communication for coherency between the caches is simplified. [Reference numerals] (100,AA,CC) Processor core; (200,BB,DD) Cache; (300) Coherency bus arbiter; (310) Coherency bus; (400) Memory; (410) Memory bus |
