发明名称 |
CHARACTERIZATION BASED BUFFERING AND SIZING FOR SYSTEM PERFORMANCE OPTIMIZATION |
摘要 |
A method for timing optimization of an integrated circuit design using a timing optimization system comprising loading an original delay value and an original gate configuration net-list for an original gate from a results database. A near optimum gate configuration is identified using near optimum gate configuration information stored in a delay characterization database for the original gate. A near optimum delay value and a near optimum gate configuration net-list of a near optimum gate configuration are loaded. A timing optimized gate configuration is provided from running an incremental static timing analysis of the near optimum gate configuration. |
申请公布号 |
US2014089879(A1) |
申请公布日期 |
2014.03.27 |
申请号 |
US201213625377 |
申请日期 |
2012.09.24 |
申请人 |
NAGRATH ANUP;MATHUR SANJIV;ATRENTA, INC. |
发明人 |
NAGRATH ANUP;MATHUR SANJIV |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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