| 摘要 |
An L2 cache control unit searches for a cache memory according to a memory access request which is provided from a request storage unit 0 through a CPU core unit, and retains in request storage units 1 and 2 the memory access request that has a cache mistake that has occurred. A bank abort generation unit counts, for each bank, the number of memory access requests to the main storage device, and instructs the L2 cache control unit to interrupt access when any of the number of counted memory access requests exceeds a specified value. According to the instruction, the L2 cache control unit interrupts the processing of the memory access request retained in the request storage unit 0. A main memory control unit issues the memory access request retained in the request storage unit 2 to the main storage device. |
