| 摘要 |
An electronic counter comprising a sequence of memory cells, each memory cell being non-volatile and supporting a one state and a zero state, the counter being configured to represent at least part of a current counting-state of the counter as a pattern of one and zero states in the memory cells of the sequence of memory cells, and increment logic configured to advance the pattern of one and zero states to a next pattern to represent an increment of the counter, the increment logic comprising programming increment logic and erasing increment logic, the increment logic being configured to alternate between a programming phase in which the programming increment logic advances the pattern, and an erasing phase in which the erasing increment logic advances the pattern, wherein the programming increment logic is configured to program a next cell of the sequence of non-volatile memory cells from a zero state to a one state, the program phase terminating when all memory cells of the sequence of memory cells are in the one state, the erasing increment logic is configured to erase a next cell of the sequence of non-volatile memory cells from a one state to a zero state, the erase phase terminating when all memory cells of the sequence of memory cells are in the zero state. |
