发明名称 DELTA-SIGMA MODULATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a delta-sigma modulation circuit that, if an output of the delta-sigma modulation circuit is saturated, can prevent an oscillating state, return to a normal operation quickly when a normal operating range is recovered, and maintain an analog-digital conversion operation in the meantime.SOLUTION: A delta-sigma modulation circuit 42 includes: an nth order loop filter comprising n (n≥3) integrators 11, 12, 13 connected in a cascade; a quantizer 17; and at least one digital-analog converter 14, 15, 16 for inputting an output of the quantizer into one of the integrators. At least n-2 of the n integrators constituting the loop filter comprise amplifiers 23, 24, 25 having a low pass filter characteristic. A determination is made as to whether or not an output of the loop filter is saturated, and if saturation is detected, the amplifiers are changed for the low pass characteristic and the order of the loop filter is reduced from the nth order to the first or second order.
申请公布号 JP2014057200(A) 申请公布日期 2014.03.27
申请号 JP20120200508 申请日期 2012.09.12
申请人 ASAHI KASEI ELECTRONICS CO LTD 发明人 UEISHI JUNPEI
分类号 H03M3/02 主分类号 H03M3/02
代理机构 代理人
主权项
地址