发明名称
摘要 <p>Pulse voltages V1 and V2 are applied to a first upper gate electrode and a second upper gate electrode, respectively, for a period T1 which is shorter than a period necessary to invert all the polarizations included in a ferroelectric film, while voltages Vs, Vd, and V3 are applied to a source electrode, a drain electrode, and a lower gate electrode film, respectively, so as to increase the values of the widths WRL1 and WRL2 and so as to decrease the value of the width WRH. The absolute values of the pulse voltages V1 and V2 are smaller than that of a voltage necessary to invert all the polarizations included in the ferroelectric film. The voltage Vs, the voltage Vd, the voltage V3, the pulse voltage V1, and the pulse voltage V2 satisfy the following relationship: Vs, Vd, V3>V1, V2.</p>
申请公布号 JP5450912(B1) 申请公布日期 2014.03.26
申请号 JP20130548513 申请日期 2013.05.22
申请人 发明人
分类号 H03K19/21;H01L21/8246;H01L27/105;H01L45/00;H01L49/00 主分类号 H03K19/21
代理机构 代理人
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