发明名称
摘要 PROBLEM TO BE SOLVED: To provide a performance estimation device capable of estimating the performance of a board to be evaluated at a high speed and high accuracy even before accomplishment of the board. SOLUTION: An instruction set simulator that simulates central processing unit only comprises an instruction set simulator (402) that calculates by simulating the number of execution cycles of the central processing unit in an entire measurement period of a program; a logic emulator (403) that emulates the central processing unit and peripheral circuits for calculating the number of execution cycles of the central processing unit during a part of measurement period of the program by emulation; and a performance estimation section (800) that calculates an estimation function based on the number of execution cycles calculated by the instruction set simulator and the number of execution cycles calculated by the logic emulator to estimate the number of execution cycles in an unmeasured period of the program in the logic emulator. COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP5454349(B2) 申请公布日期 2014.03.26
申请号 JP20100110542 申请日期 2010.05.12
申请人 发明人
分类号 G06F11/28;G06F11/34 主分类号 G06F11/28
代理机构 代理人
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