| 摘要 |
A scalable and efficient array encryption architecture is provided for encrypting data with a cryptographic algorithm using a variable number of encryption cores. The architecture can be implemented as circuitry in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD). An input arbitration logic circuit may schedule timeslots within the encryption cores to maximize system bandwidth. Each one of the encryption cores may use a plurality of pipelined registers and may support simultaneous encryption operations of multiple data blocks. Each core may provide timeslot availability signals to indicate current or anticipated availability of a timeslot for processing data in that core. The same top-level design may be used for different choices of processing depth, parallelism level, and/or system throughput. |
