| 发明名称 |
Use of silicide block process to camouflage a false transistor |
| 摘要 |
A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable. |
| 申请公布号 |
US8679908(B1) |
申请公布日期 |
2014.03.25 |
| 申请号 |
US20070932169 |
申请日期 |
2007.10.31 |
| 申请人 |
CHOW LAP-WAI;CLARK, JR. WILLIAM M.;HARBISON GAVIN J.;BAUKUS JAMES P.;HRL LABORATORIES, LLC;RAYTHEON COMPANY |
发明人 |
CHOW LAP-WAI;CLARK, JR. WILLIAM M.;HARBISON GAVIN J.;BAUKUS JAMES P. |
| 分类号 |
H01L21/338;H01L23/58;H01L27/02 |
主分类号 |
H01L21/338 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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