发明名称 System and method for fault sensitivity analysis of mixed-signal integrated circuit designs
摘要 A apparatus and method for conducting fault sensitivity analysis of the analog portions of a mixed signal circuit design includes simulating the fault free circuit design, inserting a fault into the analog portion of the circuit design, simulating the circuit design with the fault during a fault interval time period, and determining whether the fault is detectable.
申请公布号 US8683400(B1) 申请公布日期 2014.03.25
申请号 US201213683810 申请日期 2012.11.21
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 O'RIORDAN DONALD J.;YUSIM ILYA;LIU ZHIPENG
分类号 G06F9/455;G06F17/50 主分类号 G06F9/455
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