发明名称 HIGH SPEED DUAL MODULUS DIVIDER
摘要 Described is an apparatus comprising a plurality of logic units arranged in a ring, wherein an output terminal of each logic unit from the plurality of logic units is coupled to an input terminal of a next logic unit from the plurality of logic units, wherein the plurality of logic units includes a first multiple input logic unit having input nodes coupled to at least two output terminals of logic units from the plurality of logic units; and a plurality of latch units coupled to the output terminals of the plurality of logic units.
申请公布号 US2014079177(A1) 申请公布日期 2014.03.20
申请号 US201213619090 申请日期 2012.09.14
申请人 LI SHENGGAO 发明人 LI SHENGGAO
分类号 H03K23/40;H03K3/037 主分类号 H03K23/40
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