| 摘要 |
This clock data recovery device (1) generates a recovered clock and recovered data on the basis of a data in, and is provided with a signal selection unit (10), a phase delay unit (20), a time measurement unit (30), a phase selection unit (40), an edge detection unit (50), a polarity detection unit (60), a logic inversion unit (70), and a data output unit (80). The signal selection unit (10), the phase delay unit (20), the time measurement unit (30), and the phase selection unit (40) configure a clock-generating device (1A). The phase delay unit (20) includes a plurality of delay elements (211 to 21P) in a cascaded connection. The phase selection unit (40) selects the signal output from the delay element at a position corresponding to a unit interval time among the delay elements (211 to 21P), and outputs the result as a feedback clock. |
