发明名称 VERTICAL GATED ACCESS TRANSISTOR
摘要 A method of forming an apparatus includes forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The shallow trenches and the deep trenches are parallel to each other. A layer of conductive material is deposited over the first region and a second region of the substrate. The layer of conductive material is etched to define lines separated by gaps over the first region of the substrate, and active device elements over the second region of the substrate. The second region of the substrate is masked and the lines are removed from the first region of the substrate. Elongate trenches are etched where the lines were removed in the while the second region of the substrate is masked.
申请公布号 US2014077295(A1) 申请公布日期 2014.03.20
申请号 US201314086147 申请日期 2013.11.21
申请人 MICRON TECHNOLOGY, INC. 发明人 JUENGLING WERNER
分类号 H01L27/088;H01L29/78 主分类号 H01L27/088
代理机构 代理人
主权项
地址