| 摘要 |
The invention comprises sample-and-hold circuit and digital-to-analog converter into a differentially operational unit. In analog-to-digital conversion unit, on the premise of fixed or non-fixed quantization error, analog-to-digital converter dynamically adjusts number of bits solved or size of quantized step according to the magnitude of differential voltage between sampled input signal and previously quantized input signal, thus this invention can reduce the non-necessary power consumption from redundant code and overload of input signal. Differentially operational unit and analog-to-digital unit share the same capacitor array which has binary-weighted arrangement to reduce circuit complexity and area. |
