| 摘要 |
PROBLEM TO BE SOLVED: To rapidly perform barrier synchronization, while assuring the security of respective programs. SOLUTION: A computer includes a processor having one or more processor cores with one or more hardware threads. The processor cores have a plurality of privilege levels including a user mode. A plurality of hardware threads are divided into one or more groups. The hardware thread with the privilege level higher than the user mode sets information of the group in barrier domain definition information. The hardware threads in the group are divided into one or more synchronizing groups within the group. Information of the synchronizing groups is set in barrier group definition information when the hardware threads are in the user modes. Barrier point arrival information, which indicates the arrival of each hardware thread at a barrier point, is received. Then, success or failure is determined concerning the barrier synchronization in the hardware thread, based on the information of the synchronizing groups of the barrier group definition information and the groups of the barrier domain definition information. COPYRIGHT: (C)2011,JPO&INPIT |
