发明名称
摘要 An integrated circuit memory device includes a memory cell array comprising memory cells having respective data storage regions therein, a plurality of pass transistors having different channel widths and/or channel lengths, and a plurality of conductive lines. Each of the conductive lines electrically couple a respective one of the pass transistors to ones of the memory cells. Each of the memory cells has a line resistance defined by a portion of the corresponding one of the conductive lines extending between the memory cell and the pass transistor coupled thereto. Ones of the memory cells having greater line resistances are coupled to ones of the pass transistors having greater channel widths and/or shorter channel lengths than ones of the memory cells having smaller line resistances. Each of the memory cells may also include a diode therein, and ones of the memory cells having greater line resistances may include diodes having lower resistances. Related devices are also discussed.
申请公布号 JP5448953(B2) 申请公布日期 2014.03.19
申请号 JP20100061409 申请日期 2010.03.17
申请人 发明人
分类号 G11C13/00;G11C11/15 主分类号 G11C13/00
代理机构 代理人
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