发明名称 |
DEVICE CONFIGURED TO SWITCH A CLOCK SPEED FOR MULTIPLE LINKS RUNNING AT DIFFERENT CLOCK SPEEDS AND METHODS FOR SWITCHING THE CLOCK SPEED |
摘要 |
A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports. |
申请公布号 |
KR101375799(B1) |
申请公布日期 |
2014.03.19 |
申请号 |
KR20127015103 |
申请日期 |
2010.12.10 |
申请人 |
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发明人 |
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分类号 |
G06F1/06;G06F1/10;G06F13/40 |
主分类号 |
G06F1/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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