发明名称 Cable redundancy and failover for multi-lane PCI express IO interconnections
摘要 Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device. In response to detecting the failure in the first link, at an IO device end, the first set of lanes is switched with the second set of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device over the second link using the second set of lanes.
申请公布号 US8677176(B2) 申请公布日期 2014.03.18
申请号 US20100959981 申请日期 2010.12.03
申请人 BUCKLAND PATRICK A.;HERRING JAY R.;NORDSTROM GREGORY M.;THOMPSON WILLIAM A.;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BUCKLAND PATRICK A.;HERRING JAY R.;NORDSTROM GREGORY M.;THOMPSON WILLIAM A.
分类号 G06F11/00 主分类号 G06F11/00
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