发明名称 Power cut-off technique for semiconductor device
摘要 Disclosed here is a semiconductor integrated circuit device configured to suppress a voltage drop over the route for transmitting voltages from a power cut-off switch to a power cut-off region without lowering the degree of freedom in routing signal wires in that region. The semiconductor integrated circuit device includes a semiconductor chip in which the power cut-off switch and power cut-off region are provided. A reduction in the number of wiring channels in the power-cut off region is avoided by locating the power cut-off switch outside the power cut-off region. Over the substrate, a substrate-side feed line is formed to transmit a power-supply voltage from the semiconductor chip to outside thereof via the power cut-off switch, before introducing the voltage again into the chip to feed the power cut-off region, thus suppressing the voltage drop between the power cut-off switch and the power cut-off region.
申请公布号 US8674756(B2) 申请公布日期 2014.03.18
申请号 US201213538052 申请日期 2012.06.29
申请人 OYAMA MASAAKI;RENESAS ELECTRONICS CORPORATION 发明人 OYAMA MASAAKI
分类号 H01L25/00 主分类号 H01L25/00
代理机构 代理人
主权项
地址