Method and system for correcting error in a PLL generated clock signal using a system clock of lower frequency and/or accuracy

摘要

The present invention provides a system for detecting timing characteristics of internal signals in a communications device, the system comprising: a system clock running at a known frequency; a test counter having a test input at which an internal signal to be tested is received; a gating counter having an input arranged to receive the system clock signal; and a system controller for controlling the counters; wherein the system controller controls the gating counter to count a predetermined number of system clock cycles to define a test period, and during the test period the test counter counts the cycles of the internal signal under test, whereby timing characteristics of the internal signal may be found with reference to a time base defined by the system clock. An associated method of operation is also described.