发明名称 |
Device including a plurality of memory banks and a pipeline control circuit configured to execute a command on the plurality of memory banks |
摘要 |
A semiconductor device includes a delay buffer, and a pipeline control circuit. The pipeline control circuit controls the delay buffer to hold read data from outputting to a read/write bus for each of banks based on a read command to the each bank while the pipeline control circuit controlling the delay buffer to output write data to the read/write bus, when a next command to the each bank is a write command for the write data. The read/write bus is common to the banks. |
申请公布号 |
US8675419(B2) |
申请公布日期 |
2014.03.18 |
申请号 |
US20110929126 |
申请日期 |
2011.01.03 |
申请人 |
KAJIGAYA KAZUHIKO;SEKIGUCHI TOMONORI;ONO KAZUO;ELPIDA MEMORY, INC. |
发明人 |
KAJIGAYA KAZUHIKO;SEKIGUCHI TOMONORI;ONO KAZUO |
分类号 |
G11C7/10 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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